Fig. 2
Architecture and performance of Logic gates. a The different currents under the read voltage of –1 V and 1 V. b Schematic of “AND” logic gate and “OR” logic gate. (In1 is the read voltage, and the In2 is the UV light of 254 nm.) c The “AND” logic gate truth table, In1 is the read voltage of –1V (“1”) or –0.1 V (“0”), and In2 is the UV light of ON/OFF. d The typical result, and (e) the experimental results of the “AND” logic gate in 20 cycles. f The “OR” logic gate truth table, In1 is the read voltage of 1 V (“1”) or 0.1 V (“0”), and In2 is the UV light of ON/OFF. g The typical result, and (h) the experimental results of the “OR” logic gate in 20 cycles
