Fig. 9: Positive bias temperature stress (PBTS) induced threshold voltage shifts in a-IGZO TFTs.
From: Model representation in amorphous metal oxide thin-film transistors: a critical review
a, b Dependence of threshold voltage shift (∆Vth) on temperature (T) and gate-source voltage (VGS) for electrons trapped in shallow trap states under PBTS at VGS = 40 V, VDS = 0 V, and 80 °C. c, d Dependence of ∆Vth on temperature and VGS for electrons trapped in deep trap states under PBTS at VGS = 40 V, VDS = 0 V, and 80 °C120. a Shallow trap, Vgs = 40 V, Vds = 0 V: blue (80 °C), red (60 °C), black (40 °C). b Shallow trap, Vds = 0 V, 80 °C: blue (Vgs = 40 V), red (30 V), black (20 V). c Deep trap, Vgs = 40 V, Vds = 0 V: blue (80 °C), red (60 °C), black (40 °C). d Deep trap, Vds = 0 V, 80 °C: blue (Vgs = 40 V), red (30 V), black (20 V). Lines: Model; symbols: Extracted data.
