Table 2 Participation ratios for various qubit structures.

From: Surface loss calculations and design of a superconducting transmon qubit with tapered wiring

Interface

Eqs.

MA

MS

SA

Parallel plate

(8)

8.16e−5

  

Ribbon

(49)–(51)

1.04e−6

1.42e−4

2.74e−5

Coplanar

(57)–(59)

1.04e−6

1.42e−4

2.74e−5

Straight wires

(76)–(80)

7.47e−7

1.02e−4

1.30e−5

Tapered wires

(84)–(88)

2.35e−7

3.22e−5

4.90e−6

  1. The top three are for the primary qubit capacitance, and the bottom two are for straight and tapered wires that connect to the junction with capacitance ~ 7 fF. For comparison purpose, they all use a length ℓ such that the total capacitance is 100 fF. Geometry parameters are thickness t = 0.1 μm; parallel plate (s, w, ℓp) = (5, 100, 1130) μm; ribbon and coplanar (a, b, ℓr, ℓc) = (50, 100, 1391, 1138) μm; junction wires \((2d,\overline{r},{\overline{r}}_{0})=(100,0.1,0.1)\,\mu {{{\rm{m}}}}\) and S = 0.4. Dielectric parameters are (ϵs, ϵMA, ϵMS, ϵSA) = (11.7, 9.8, 9.8, 3.8). For simplicity, here the oxide thickness is assumed to be tMA = tMS = tSA = 2 nm; results can be simply scaled with expected thickness. Total loss can be estimated by multiplying the surface loss tangents10; typical values for amorphous insulators are 0.00514.
Back to article page