Fig. 6: Circuit for error correction of 1D Abelian LGT with dynamical fermions.
Circuit for using information from Gauss’ law checks \({{{{\mathcal{G}}}}}_{2k}\) and \({{{{\mathcal{G}}}}}_{2k+1}\) on S2k, S2k+1, and their adjacent links to correct bit-flip errors on them. Bit-flip errors on even-numbered links can be corrected using the information obtained from one such check. Bit-flip errors on sites and odd-numbered links require information from two such checks to be corrected. See Fig. 7b for the corresponding syndrome outcomes.
