Fig. 1: The qubit pipeline.
From: Pipeline quantum processor architecture for silicon spin qubits
a In a typical N-qubit solid state quantum processor, qubits reside at fixed spatial locations (e.g. on a \(\sqrt{N}\times \sqrt{N}\) grid) with nearest-neighbour connectivity. b The qubit pipeline is a weaved grid in which N qubits are shuttled through D locations where fixed single- (1Q) or two-qubit (2Q) logic gates are implemented. Vertical lines indicate 2Q couplers, while horizontal lines indicate shuttling couplers. At runtime, qubits are initialized at one end, synchronously shuttled through the pipeline, and read out on the opposite end. c An example quantum circuit diagram, where an algorithm is decomposed into alternating steps of 1Q and 2Q gates. d–f The qubit pipeline contains physical locations which have been configured to implement 1Q (circles) and 2Q (connected circles) gates. Different qubit arrays (first (χ0, χ1, . . . ), then (ψ0, ψ1, . . . ), (φ0, φ1, . . . )) can be piped sequentially through the structures, each representing one execution of the configured quantum circuit.
