Table 1 Comparison between the quantum lattice and the pipeline processors

From: Pipeline quantum processor architecture for silicon spin qubits

 

Lattice

Pipeline

Processor size

\(\sqrt{N}\times \sqrt{N}\)

N × D

Run-time control resources

N

constant

Circuit decomposition

flexible

limited

Run-time scaling

DNr

D + Nr

  1. Here, N is the number of qubits, D is the maximum circuit depth, and Nr is the number of repetitions.
Back to article page