Fig. 1: Device architecture and charge control. | npj Quantum Information

Fig. 1: Device architecture and charge control.

From: Industrial 300 mm wafer processed spin qubits in natural silicon/silicon-germanium

Fig. 1

a 3D model of the device. 3-layer TiN gate architecture (orange, blue, red) on the SiGe heterostructure (cyan and green). SiO2 (grey) insulates the different layers from each other. The electron gas is formed in the buried Si layer. The CoMM (violet) is encapsulated by a SiO2 passivation layer, and all structures are connected by vias (yellow). b False coloured scanning electron microscopy image with included gate labelling and schematic display of later formed electron reservoirs and quantum dot positions. The CC gate will be pulsed with RF microwaves and the arrows indicate the direction of the oscillating quantum dot positions and the current path of the sensor dot. c Coulomb oscillations of the right qubit dot, formed below gate PR. Red dots indicate the 4 positions used to extract values for charge noise. d Calculated power spectral density of a 5 min timetrace taken at the indicated working point. A mean 1 Hz value of (1.36 ± 0.07) μeV/\(\sqrt{{\rm{Hz}}}\) is extracted. The black line follows a 1/f proportionality. e Charge stability diagram of the two coupled qubit quantum dots, measured via charge sensing by the sensor dot. Both qubit plunger gates are swept and every visible line corresponds to a change of electron number in the respective dots, starting with a (0,0) occupation in the lower left.

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