Extended Data Fig. 1: Schematics illustrating the fabrication steps of the 3D FET array.
From: Three-dimensional transistor arrays for intra- and inter-cellular recording
a, The FET’s drain, source, and gate regions are determined on an n-type SOI wafer by doping. First, the undoped region (that is, the region with only the background doping from the wafer) is coated by a layer of SiO2 as the barrier for spin-on dopants from diffusing into the silicon substrate. Second, the FET shape is defined by photolithography and reactive ion etching. b, The FETs are firstly anchored to the substrate by PTFE, and then are transferred using a PDMS stamp to a temporary 2D substrate coated with PI. c, Multi-layered polymers and metal are coated and patterned on the temporary substrate. Finally, the layered device is transferred to a PDMS stamp and picked up by a water-soluble tape. d, The FET array is transferred to a prestrained elastomer substrate and selectively bonded at the two pre-designed bonding sites. When the prestrain releases, the 2D FET array gets compressed and buckled up to form 3D geometries.
