Extended Data Fig. 3: Optimizing the FETs’ electrical properties by tuning doping concentrations.
From: Three-dimensional transistor arrays for intra- and inter-cellular recording
a, Sheet resistances of (i) antimony doped SOI (N-type) and (ii) boron doped SOI (P-type) wafers, determined by high-temperature doping with phosphorus dopant (P509) at 950 °C for various doping times (Δt), which is defined as the period that the apex temperature was held during annealing. b, A typical temperature profile for driving the phosphorus dopants into the SOI wafer. The most effective doping period was at the highest temperature (950 °C), as indicated by Δt. A longer Δt generates a smaller sheet resistance of the SOI. We applied a two-step doping process: the first light doping was for the whole SOI that determined the FET’s conduction channel’s doping concentration; and the second heavy doping was for the whole SOI except the conduction channels. The resultant FET had an N+NN+ structure and worked under a depletion mode. c-e, Transfer characteristics of devices by various doping conditions, including (c) undoped, (d) selectively doped, and (e) heavily uniformly doped sensors. f, Transfer characteristics of (i) p-type and (ii) n-type depletion-mode FETs, showing that the n-type FETs demonstrate about six times larger transconductances (that is, sensitivities) than those p-type FETs. Therefore, we chose n-type depletion-mode FETs in this work.
