Extended Data Fig. 3: Supplementary data for wafer scale uniformity.
a, Optical image of one back-gate MoS2 transistor on Al2O3/Si substrate. b, Hysteresis measurement of one of the MoS2 transistors with PMMA passivation. The gate voltage was swept from −2 V to 7 V (blue curve), and from 7 V to −2 V (red curve). The sweep speed is around 55 mV/sec with VDS = 0.7 V. The measurement was carried out in dark and ambient condition. c, Peak position mapping of the photoluminescence (PL) data over the 8-inch wafer. d, Integrated intensity mapping of the PL data over the 8-inch wafer. The color represents the integrated intensity of the peak from 1.82 eV to 1.90 eV photon energy. 100% refers to the highest integrated intensity of the monolayer MoS2 thin film measured over the 8-inch wafer. e, Optical image of the 8-inch wafer with fabricated MoS2 transistors. 300 nm SiO2/Si substrate was used as the global back gate structure. f, On-state resistance mapping of back-gated MoS2 transistors over 8-inch wafer. g, 4 MoS2 transistors which can represent the typical performance of transistors in the center region on 4 different 8” wafers.
