Extended Data Fig. 1: Double-gated bilayer (2 L) CrPS4 field effect transistor (FETs).
a-c, Optical microscope images of the 2 L CrPS4 FET whose data is shown in the main text, at different stages of fabrication. a, Exfoliated 2 L CrPS4 crystal on top of a 285 nm SiO2/Si substrate. b, h-BN/ CrPS4 /graphite (Gr)/h-BN heterostructure assembled via a dry-pick up and transfer technique within the protective environment of a glovebox. The graphite stripes serve as electrodes for the transistor, and the top and bottom h-BN crystals encapsulate the 2 L CrPS4 to protect it from the environment during subsequent fabrications steps outside the glovebox. c, Completed double-gated FET. Electron-beam lithography and evaporation are used to fabricate the Cr/Au metal layers serving as contacts to the Gr electrodes (edge contacts) and as top-gate electrode (top h-BN serves as top-gate dielectric). The bottom gate electrode is the highly doped Si substrate and the bottom gate dielectric is composed by the 285 nm SiO2 layer together with the bottom h-BN crystal. d-e, Atomic force microscope height profile of the top and bottom h-BN crystals. f, g, Transfer curves measured at 2 K as a function of bottom (top) gate voltage VBG (VTG), while keeping the top (bottom) gate at a constant potential (at the values indicated in the figures). h, i, Back gate and top gate threshold voltage, VBGTH and VTGTH, plotted as a function of the potential applied to the opposite gate. The slope of VBGTH vs VTG in f and of VTGTH vs VBG in g are consistent with the corresponding ratios between the top and bottom gate capacitances. The threshold voltage values in h (i) are extracted by extrapolating the linear regime of the transfer curves shown in f (g) to zero current Source data.
