Fig. 1: Perovskite hardware for efficient data processing and computation on the same wafer.

a, Schematic of the computational framework, consisting of two distinct layers: a dynamic spatiotemporal processing layer and a static output layer. The equations at the bottom describe the evolution of the state x(t) and the computation of the output y(t), demonstrating the dynamic nature of the spatiotemporal processing layer’s response and the linear mapping in the output. b, Schematic of the corresponding hardware implementation integrated on a single NdNiO₃/LaAlO₃ substrate. The time-dependent input signals u(t) proportionally converted into voltage spike trains V(t) are applied directly to catalytic Pd electrodes on a H-NNO film. The resulting output current x(t) from each electrode is monitored as the output of the spatiotemporal processing layer. c, Photograph of the fabricated chips with single device, spatiotemporal processing layer and linear output layer units. d, Microscope image of spatiotemporal processing arrays. Scale bar, 100 μm. e, Zoomed-in scanning electron microscopy image of spatiotemporal processing units. Scale bar, 5 μm. The distance between each Pd electrode is 3.5 μm. f, Microscope image of output layer arrays. Scale bar, 250 μm. g, Zoomed-in scanning electron microscopy image of a single device unit for output layer. Scale bar, 5 μm. h, Schematic of the Pd–Pd nickelate devices, where one hydrogen cloud expands while the other shrinks, exhibiting time-dependent hydrogen redistribution and charge relaxation. i, A schematic of the Pd–Au nickelate devices with hydrogen cloud migration from the Pd electrode enabling non-volatile resistance change.