Extended Data Fig. 2: Fabrication steps for SCMs with depressed barriers, and scanning electron microscopy images of representative SCMs.

a, Silicon wafers are processed by standard photolithography and multiple steps of deep reactive-ion etching (DRIE). Specifically, a 1.2-µm-thick AZ 6612 photoresist layer is patterned (step 1) to mask the SiO₂ layer during etching in buffered hydrofluoric acid (BHF; step 2). A new layer of AZ 6621 is patterned (step 3), exposing the areas that are etched to form the trenches during the first DRIE step (step 4). Later, using the patterned SiO₂ layer as the mask, a second DRIE step forms the microchannels while preserving the trenches (step 5). After dicing, the chips are cleaned and silanized in trichloro(octyl)silane solution (step 6). After reagent deposition, chips are sealed with a layer of polydimethylsiloxane (PDMS; step 7). b, Image of an SCM fabricated in silicon, with yellow frames highlighting particular regions shown below. c, The leading barrier with a trench geometry. Here, for visual clarity, the trench width is 20 µm, but 5-µm-wide trenches were used in experiments. The curved end of the leading barrier facilitates the initiation of self-coalescing flow. d, Diversion barrier with a step-down geometry. e, Raised vertical CPLs at the entrance of the SCM help to keep the meniscus away from the side wall coloured in blue. f, The barrier at the vent entrance (arrowhead) ensures that liquid does not enter the vent. The depths of the SCM (H_SCM), outlet (H_outlet) and barriers (H_barrier) are shown on the images. g, h, Scanning electron microscopy (SEM) images of the devices used in G6PDH reactions (g) and in RPA reactions (h). (The numbers 1-2 and 1-4 are device numbers.).