Extended Data Fig. 9: The TCAD simulation results of the 0.34 nm gate-length side-wall transistors to boost On-state performance. | Nature

Extended Data Fig. 9: The TCAD simulation results of the 0.34 nm gate-length side-wall transistors to boost On-state performance.

From: Vertical MoS2 transistors with sub-1-nm gate lengths

Extended Data Fig. 9

The transfer curves by scaling down Lch from 500 nm to 4.54 nm shown in (a) log-scale and (b) linear-scale. The transfer curves under extreme Lch = 4.54 nm with different fixed Al bias shown in (c) log-scale and (d) linear-scale. The transfer curves under extreme Lch  = 4.54 nm by scaling down gate dielectric thickness from 14 nm to 5 nm shown in (e) log-scale and (f) linear-scale. Under 14 nm HfO2 as gate dielectric, VBS = 50 V, VAl = 0 V and VDS = 50 mV condition, the On-state current can be further improved ~2 orders of magnitude.

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