Fig. 2: Maximum-current-alignment scheme of the quantum dot array using only six in-plane gates.
From: Engineering topological states in atom-based semiconductor quantum dots
a, An STM micrograph of device I, which shows the six control gates, labelled G1 to G6, used to tune the energy levels of the quantum dots to observe the conductance peaks using bias spectroscopy. Here we can observe the atomic step height of the silicon surface and the nanoscale size of the array. b, Schematic of the protocol used to align the quantum dots in the array. The quantum dots can be brought into alignment by varying the voltages applied to the control gates to tune the quantum dots for maximum current through the array. Each control gate is initially set to a specific value, chosen from a conductive region from the current map (red circle) while changing gates G1–G3 and G4–G6 together. The voltage on each gate is then swept, in turn, around their respective maximum current values, while the other gates are kept constant. After all gate voltages have been swept, a single gate value is then updated corresponding to the maximum current measured. The process is then repeated updating one gate each time. When the maximum current saturates, the source–drain bias, VSD, is then reduced and the control gates are retuned again to increase the maximum current. Once the VSD is near zero, a stability diagram is measured as shown in the top right and the zero-bias conductance (dotted white line) is used for comparison with the simulated SSH model in Fig. 3. c, Examples of the individual gate sweeps on the first iteration (top) and on the tenth iteration (bottom) for a constant VSD. d, e, The voltage on each gate per iteration (the gate updated per iteration is labelled at the bottom; d) and showing the maximum current measured on each gate sweep per iteration (e).
