Extended Data Fig. 1: Peripheral driver circuits for TNSA and chip operating modes.
From: A compute-in-memory chip based on resistive random-access memory
a, driver circuits’ configuration under the weight-programming mode. b, under the neuron-testing mode. c, under the MVM mode. d, circuit diagram of the two counter-propagating LFSR chains XORed to generate pseudo-random sequences for probabilistic sampling.
