Extended Data Table 2 Comparison with digital CMOS AI inference accelerators

From: A compute-in-memory chip based on resistive random-access memory

  1. Notes:
  2. 1. The method to project NeuRRAM efficiency to 7 nm is explained in Methods.
  3. 2. The energy-efficiency projection of digital accelerators is based on CV2 scaling, where C scales with minimum metal pitch and V is adjusted to nominal VDD of 7 nm.
  4. 3. The area-efficiency projection of digital accelerators is based on minimum metal pitch scaling along both horizontal and vertical directions.
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