Extended Data Fig. 7: Inner spacer structure and TCAD simulation.

a, Schematic diagram of a proposed process to achieve self-aligned (overlap-free) double-gate structure with low-k inner spacer and the process is compatible with the Y-doping ohmic contact. b,c, TCAD simulation of electron density distribution on the extension surfaces between the gate and the source/drain in ballistic InSe FETs with different k of the spacer. d, Schematic diagram of the ballistic InSe FETs with and without overlap from TCAD. e, The TCAD simulations of transfer curves of ballistic InSe FETs with (red) and without (black) overlap. f, On-state current density versus doping concentration of the ungated region below the spacer.