Extended Data Fig. 7: MLPerf RNNT Decoder mapping and signal routing on chip.
From: An analog-AI chip for energy-efficient speech recognition and transcription
Instead of processing Embedding Emb and Dec-LSTM0 Wx layers separately, we first compress in one single matrix the product Emb * Wx. At this point, the first Dec-LSTM0 shows Emb * Wx matrix with a (28*1280) size, contrasting with the (320*1280) Wh size to sum directly in analog. To balance signal magnitude, nine copies of Emb * (Wx/9) are programmed, achieving comparable weight absolute magnitudes. (b) Weight mapping and (c) signal routing implementing Asymmetry Balance. Routing from tiles to Output Landing Pads utilizes implicit vector concatenation on the 2D mesh, enabling more efficient data transport. (d) The processing of one full frame requires 5 time steps of 300 ns each.
