Extended Data Fig. 7: SS distribution and hysteresis of vdW-transferred c-Al2O3 top-gate MoS2 transistors.
From: Single-crystalline metal-oxide dielectrics for top-gate 2D transistors
a, Transfer curves of top-gate MoS2 transistor. b, SS distribution as a function of channel current in a. The dashed line represents the thermal limit of SS at room temperature (60 mV/dec). c, The double-sweep transfer curves with different step size and sweeping rates of MoS2 transistor using the transferred c-Al2O3/Al gate stack. d, Hysteresis versus sweep rate.
