Fig. 3: The cross-platform compatibility verification methodology.
From: A full-featured 2D flash chip enabled by system integration
a, Schematic showing the 2D module design and 2D-compatible CMOS modules design for realizing a 2D flash memory chip. b, The Si device design in the power switch module for voltage domain compatibility with 2D flash. The isolation ring decouples source–drain from the p-substrate, allowing local negative voltage biasing. A supplemental buried N-well improves voltage tolerance for 2D flash operation. c, The 2D compatible inverter chain design within the buffer modules. Stage count and driver ratio were optimized on the basis of 2D flash load capacitance and CMOS inverter input capacitance. The output waveforms under different driver abilities were simulated by adjusting the transistor W/L ratio in the final inverter. d, Sense amplifier design optimization and readout characterization. Data sequence ‘0101’ across four WLs is simulated for reading. The BL parasitic capacitance leads to misreading of SA1 (for details, see Extended Data Fig. 4). SA2 achieves correct reading by isolating the BL parasitic capacitance and further improves readout speed by reducing the load of the readout circuit (for details, see Extended Data Fig. 5). e, Timing diagram of programming operation. The operation instructions include 8-bit commands (06H, 02H, where H represents hexadecimal), address and 4 data bytes. WL[22] is accessed for programming, and 32-bit input data is programmed in parallel to WL[22]. CS, chip select signal; SPI_SCLK, serial clock of the Serial Peripheral Interface protocol; SPI_SI, serial data input of the SPI protocol; addr, address; din, data input; clk, clock; GND, ground.
