Fig. 4: Full function demonstration based on full-chip test.
From: A full-featured 2D flash chip enabled by system integration
a, Schematic of the chip test system. The AWG and d.c. power supply provide the required external clock signals (OSC) and d.c. signals, respectively. The FPGA transmits the command and data between the host computer and the I/O ports of the 2D flash chip, including the CS, SCLK, serial data input (SI) and serial data output (SO). The oscilloscope monitors pulse waveforms generated by the AWG. b, Data flow of the 2D flash chip. Modules are labelled in rectangular boxes, whereas the flow of key signals is indicated by arrows. c, Histogram of the programming accuracy across the 32 WLs after checkerboard programming. About 93.55% of cells reach the target states corresponding to the checkerboard pattern. dout, data output; rd_clk, read clock; rdbl, read bit line.
