Extended Data Fig. 2: Retention performance for 2D flash cell with HfO2 tunnelling layer.
From: A full-featured 2D flash chip enabled by system integration
Vth shift for state-ON (a) and state-OFF (b) at 55 °C, 85 °C and 125 °C are extracted by the Vth difference between as-programmed cell and cell after baking to present the retention loss. c, Total memory window with different bake temperature and time. The memory window considers both the retention loss from state-ON and state-OFF in (a) and (b). When MW lost by half, the cell is determined to fail. d, the temperature of retention lifetime extrapolated from (c). A 10 years lifetime at 54.8 °C is extracted with Arrhenius model.
