Extended Data Fig. 5: Circuit schematic of SA module with 2D compatible design (SA2) (a) and corresponding reading simulation results (b).
From: A full-featured 2D flash chip enabled by system integration
A switch transistor (MN7) is introduced to isolate the high capacitance load from the 2D memory array. Therefore, the capacitance couple effect is weakened, and VBL is only coupled to 3.038 V, which considerably reduces the time required for VBL discharging. The fast and accurate cell state readout is achieved. Besides, the CMOS inverter (corresponding to INV1 in Extended Data Fig. 4) is substituted with a pseudo-PMOS inverter, which can reduce the SA load capacitance, for better operation mode compatibility and lower propagation delay time.
