Extended Data Fig. 4: Gallery of 3-cm 3D architectures with sub-micrometre resolution.
From: 3D nanolithography with metalens arrays and spatially adaptive illumination
a, A LLNL logo with some focal spots turned off. A central processing unit chip is placed underneath for size reference. b, LLNL logos and a Stanford logo. A 6-inch wafer is placed underneath for size reference.
