Fig. 2: CMOS compatibility and process flow of Ge-silica ultralow-loss PICs. | Nature

Fig. 2: CMOS compatibility and process flow of Ge-silica ultralow-loss PICs.

From: Towards fibre-like loss for photonic integration from violet to near-infrared

Fig. 2: CMOS compatibility and process flow of Ge-silica ultralow-loss PICs.

a, Schematic of fabrication workflow for ultrahigh-Q Ge-silica resonators. ALD, atomic layer deposition. b, Photograph of Ge-silica PICs on silicon at wafer scale, SEM image showing the sidewall of an annealed waveguide (intentionally overetched to show the contrast in reflow compared with non-reflowed material) and cross-section of cladded waveguides. c, Anneal-free waveguide loss (C band) compared with temperature for state-of-the-art low-loss PICs11,44,45,46,47,48,49,50 compared with the present work. CVD, chemical vapour deposition; PVD, physical vapour deposition. d, Examples of monolithic/heterogeneous integration applications of ultralow-loss anneal-free Ge-silica PICs, including co-integration with III–V materials, organic electronics/photonics, thin-film lithium niobate, thermal-engineered quartz substrates and Ge-on-silicon photodetectors. Scale bars, 500 nm (b, bottom left); 5 μm (b, bottom right).

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