Figure 1
From: STM patterned nanowire measurements using photolithographically defined implants in Si(100)
A schematic representation of the implant based contact process for STM patterned devices. For each step shown, the left is a pseudo-plan view and the right is a cross-section of the step. First (a), the heavily doped contact wires are defined by using photolithography and low energy ion implantation. Secondly, after the wafer is etched with STM alignment marks and diced, implanted chips are loaded into a UHV system for high temperature processing, H-passivation and STM lithography. The etched fiducial marks, see (b) and (c), guide the STM during its coarse positioning to locate the preimplanted wires. Upon completion of STM lithography (b), the pattern is dosed with phosphine and heated to incorporate the dopants. Note that the overlap between the STM pattern and the implant wire define the interface between the implant wire and the 2D electron gas. Then, (c) a capping layer of Si is deposited to encapsulate the device. Finally, the sample is removed from the chamber and (d) Al metal contacts are deposited and patterned by photolithography.
