Figure 4
From: Palladium gates for reproducible quantum dots in silicon
(a) AFM image of Device F with a gate pitch of 40 nm. The leftmost barrier gate was not connected. (b) plot of I versus the voltages on the barrier gates b1 and b2 with fixed Vlead = 4000 mV and VSD = 1 mV. (c) I plotted versus Vlead = 4000 mV and Vb1 = Vb2 + 300 mV at VSD = 1 mV. (d) The Coulomb peak distance ΔVb1 between adjacent Coulomb peaks at Vlead = 3500 mV. (e) Differential conductance dI/dVSD versus Vb1 at Vlead = 3500 mV. All measurements taken at 4.2 K.
