Figure 1
From: Vertical WS2/SnS2 van der Waals Heterostructure for Tunneling Transistors
(a) Schematic view of the bottom-gated vertical tunneling transistor based on 2D semiconductors. Vertical tunneling occurs across the overlap region between p-type layer and n-type layer. (b) Band alignment in the off-state (left). There is no tunneling window between the valence band of the source layer and the conduction band of the channel layer. Band alignment in the on-state (right). The electric potential and carrier concentration of the channel layer are modulated by the bottom gate, and the tunneling window exists in which electrons can tunnel from the valence band of the source layer to the conduction band of the channel layer. (c) Band diagram of the WS2/SnS2 heterostructure with Ebeff of 0.02 eV. (d) The optical microscope image of the fabricated n-type WS2/SnS2 tunneling transistor. (e) High-resolution STEM image and (f) EDS mapping of the WS2/SnS2 heterostructure. A clean and sharp interface is obtained. (g) Raman characterization of WS2 and SnS2 sheets used for tunneling transistors.
