Figure 1
From: Dynamic Concatenation of Quantum Error Correction in Integrated Quantum Computing Architecture
Schematic picture of our integrated QC architecture and dynamic concatenation. (a) An integrated QC architecture. The quantum compiler decomposes a quantum algorithm into an assembly code. The assembly code and the maximum tolerable error rate ετ are stored in a classical memory. The system organizer manages and controls logical qubits. In particular, it evaluates the concatenation level required to run the algorithm. The block of the logical qubits performs QC according to a set of logical gate operations. The physical-qubit block is responsible for the control of native gates at physical level. (b) A simple illustration of our dynamic concatenation (DC) scheme. By using our DC scheme, we can reduce concatenation level of a (logical) qubit from l to l − s. Of course, the additional processes (denoted as red boxes) for decoding and encoding should be adopted to complete the DC and it imposes the extra cost. Nevertheless, it is expected to achieve practical advantage, reduction of the overall operation time, for a sequence within a length, say N, of single (logical) qubits. Here, the effective lower and upper bound of N, which enable us to achieve the aforementioned advantage, is derived theoretically (see the main text).
