Figure 1 | Scientific Reports

Figure 1

From: Border Trap Extraction with Capacitance- Equivalent Thickness to Reflect the Quantum Mechanical Effect on Atomic Layer Deposition High-k/In0.53Ga0.47As on 300-mm Si Substrate

Figure 1

(a) Energy-band diagram of a metal/Al2O3/n-InGaAs MOS capacitor with the interface and border traps when an AC signal is applied. (b) Response regions of the interface and border traps in the capacitance-voltage (C-V) behavior of the Al2O3/n-InGaAs MOS capacitor. (c) Equivalent circuit diagram for the gate capacitance of the III–V MOSFET.

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