Figure 2

Role of fabrication strategies on the structural integrity and etch quality of VLSDI 2.0 chips using conventional approaches. (a) Schematic showing conventional TSV etching using a carrier wafer. (b) A photograph shows broken wafer in DRIE chamber that is bonded to carrier wafer using crystal bond adhesive, due to trapped air pockets between the wafers. (c) A photograph shows non uniform etching of TSVs due to non-uniform temperature across the wafer when using a carrier wafer. (d) A photograph shows a wafer that broke while being removed from the carrier wafer. The yield using a carrier wafer was 30%. (e) Schematic showing our technique to replace the carrier wafer with a PECVD SiO2 etch-stop, but where we do not include stress relief for the oxide or trenches in the delivery channel. (f) Micrograph shows broken oxide layer at underpass via positions, due to stress relief features not being included. Scale bar 100 µm. (g) Micrograph shows broken wafer at the intersection of underpass and supply channel positions due to deep etching of delivery channels (h = 460 µm), due to trenches not being included. Scale bar 500 µm. (h) Photograph shows a 3D etched wafer broken during drying with a Nitrogen gun, due to trenches not being included. The yield using this technique was 50%. (i) Schematic image showing our final robust fabrication strategy, including both the SiO2 etch-stop, stress relief, and trenches in the delivery channel. (j,k) Images show the stress relieved oxide layer and a successful via etch. Scale bars 200 µm. (l) Photograph shows successfully fabricated and bonded VLSDI 2.0 chip. The yield using this technique is 100% (M = 16 chips).