Figure 7
From: Robust Microfabrication of Highly Parallelized Three-Dimensional Microfluidics on Silicon
Schematic step by step description and 3D fabrication of VLSDI 2.0 chip in a single 4” Silicon wafer. (a) Fabrication of delivery channels. (b) Fabrication of trenches inside delivery channels. (c) Fabrication of SiO2 etch-stop layer. (d) Fabrication of underpass channels in backside of wafer. (e) Fabrication of Through Silicon Vias (TSVs). (f) Fabrication of flow focusing generators. (g) The 3D etched wafer and 4” Borofloat 33 glass wafers are anodically bonded to encapsulate the microfluidic channels. (h) Scanning electron micrograph image shows the sequential etch process of fabrication in VLSDI 2.0 chip. Scale bar 115 µm, for ease of comparison the images are not flipped.
