Figure 3

CLEAR comparison between electrical (blue) and hybrid photon-plasmon (red) on-chip interconnect links as a function of link length and technology evolution time. The chip scale (CS = 1 cm) link length and current year (2019) are denoted in red. The following models are deployed; (a) A capacity-area model based on the number of transistors and on-chip optical devices, which can be regarded as the original Moore’s Law model; (b) An energy efficiency model is derived based on Koomey’s law, which is bounded by the k_BT·ln(2) ≈ 2.75 zJ/bit, Landauer limit (k_B is the Boltzmann constant; T is the temperature); (c) A the economic resistance model based on technology-experience models and at the year 2019, the electronic link cost less than one billionth to one millionth of the cost of the hybrid link; and (d) A model for parallelism (after year 2006) capturing multi-core architecture and the limitation from ‘dark’ silicon concepts in electrical link interconnects. The yellow data point represents crossover point between two technologies in the year of 2019, where the Hybrid Plasmon-Photonics technology just passed the chip scale and starts to show better CLEAR performance for on-chip applications.