Figure 1
(A) Simplified view of whole chip with optical fibers inserted on the short edges of the chip facing each other and two capillaries inserted parallel into the long edge of the chip. (B) The Si substrate was patterned and etched using the Bosch process to form trenches at a width of 30 µm. (C) The parylene-C with thickness of ≈ 1.5 µm was deposited, and (D) the trench floor was later photo-blasted by femtosecond to expose the silicon. (E) The wafer was subjected to XeF2 vapors, removing silicon from the trench floor and thus forming a tubular channel with a diameter of ≈500 µm. (F) Parylene was stripped off using O2 plasma. (G) The wafers were diced into individual chips, and a second layer of parylene-C was deposited with a thickness of ≈ 30 µm sealing the trenches and coating sidewalls of the channels. (H) As the last step, the capillary and optical fibers were inserted into the side holes and sealed with an epoxy resin.
