Figure 1

(a) A schematic cross section view of the SOI (silicon-on-insulator) sample structure. Its front surface has a periodic surface texture and its back surface etched, leaving behind a 10 μm thick crystalline silicon; (b) a magnified schematic of the sample coated with a front ARC (antireflection) layer and a back-side SiO₂ buffer and a back reflector; (c) a photo of the front side of a 4-inch SOI wafer, having a periodic surface texture; (d) a photo of the back side of the SOI wafer, showing the etched silicon side-wall. (e) A schematic of the Inverted Pyramid Photonic-Crystal (PhC) with a lattice constant a = 2,500 nm; (f) a SEM (scanning electron micrograph) image of the fabricated Inverted Pyramid structure. A wet etch method is used to etch and expose the silicon (111) surfaces, as indicated by the black arrow. (g) A schematic of the Teepee PhC with a lattice constant a = 1,200 nm. (h) A SEM image of the fabricated Teepee PhC structure. The etched surface follows a Gaussian-like graded index profile.