Table 12 Analysis of time complexity with state of art counter parts.
From: Design of fractional evolutionary processing for reactive power planning with FACTS devices
S. no. | Reference | Specifications | Bus system | Average time (s) |
|---|---|---|---|---|
1 | SOA | Matlab 7, Pentium 4, | IEEE-57, | 391.32 |
Run=30 | CPU 2.4 GHz, 512 MB RAM | IEEE-118 | – | |
2 | SGA | Matlab 6.5, Pentium 4, | IEEE-57, | 156.34 |
Run=30 | CPU N.A, RAM N.A | IEEE-118 | 335.54 | |
3 | PSO | Matlab 6.5, Pentium 4, | IEEE-57, | 59.21 |
Run=50 | CPU N.A, RAM N.A | IEEE-118 | 144.46 | |
4 | MAPSO | Matlab 6.5, Pentium 4, | IEEE-57, | 41.93 |
Run=50 | CPU N.A, RAM N.A | IEEE-118 | 119.35 | |
5 | IEP | Pentium 3 750 | IEEE-118 | 77.35–142.8 |
6 | EP | Matlab 6.5, Pentium 4, | IEEE-14, | 72–78 |
|  | CPU N.A, 128 MB RAM | IEEE-30 | 103–118 | |
7 | SARGA | Matlab 6.5, Pentium 4, | IEEE-30, | 54–66 |
|  | CPU N.A, 128 MB RAM | IEEE-118 | 87–101 | |
8 | Proposed | Matlab 2016, Core i 7, | IEEE-30, | 42 |
Run=100 | CPU 3.4 GHz, 8 GB RAM | IEEE-57 | 55 | |
| Â | Â | IEEE-118 | 60 |
