Figure 5
From: Impact of device scaling on the electrical properties of MoS2 field-effect transistors
(a) Simulated SS versus log (ID) for a uniform layer of 1, 3 and 5 monolayers of MoS2 for SBH = 0.45 eV and 0.75 eV. For ID > 1e−9 A/μm, tunneling through Schottky barrier determines the SS. Subsequently, a thinner channel results in better gate control, shorter tunneling length and therefore better SS. (b) Probability distribution versus device dimensions (Lch x Wch). AFM from Fig. 1a was used to compute the probability distribution for fabricating devices on only 3, 4, 5 or a combination of those (mixed). Our experimental devices have a 60–70% probability of being mixed, leading to non-uniform gate control across the channel and contact regions. (c) VT,CC versus Lch for two different Wch (200 nm, 1000 nm) and VDS (0.05 V, 1 V). No VT roll-off at VDS = 0.05 V due to excellent gate control over the channel for 12 nm HfO2. VT roll-off of about 200 mV for VDS = 1 V due to higher lateral-field at the source contact allowing for more carrier injection. No systematic VT deviation between Wch = 1 μm and 200 nm. (d) Benchmark plot showing gm,max versus SSmin. All values are at VDS = 1 V except39—VDS = 0.1 V34,—VDS = 0.5 V40,—VDS = 1.2 V37,—VDS = 1.5 V. In this work, 4 nm HfO2 provides best SS = 86 mV/dec and gm,max = 185 μS/μm.
