Figure 6
From: Impact of device scaling on the electrical properties of MoS2 field-effect transistors
(a) Power performance area (PPA) analysis comparing silicon and 2D in the same configuration of 4 stacked nanosheets with gate-all-around. (b) The baseline (A) is set with experimental values, Rc = 1.5 kΩ.µm (corresponding to ΦSB = 0.45 eV), µ = 15 cm2/Vs, Dit = 3 × 1012 cm−2 eV−1, tchannel = 3 layers. For (B) the contacts are improved with Rc ≤ 50 Ω.µm (corresponding to ΦSB = 0.2 eV). For (C) the channel is further improved with µ = 200 cm2/Vs, Dit = 1 × 1012 cm−2 eV−1, tchannel = 1 layer. For (D), more aggressive improvements are done with µ = 450 cm2/Vs and no Rc. For all curves, the area is the same and the bias conditions are such that at Vdd = 0.7 V, Ioff is fixed at 2nA. Methodology from44.
