Table 1 Device parameters of the proposed 3-D stacked ADG 1 T-DRAM used for the simulation work.
Parameter | Value |
|---|---|
Main gate length (Lmg) | 70 nm |
Control gate length (Lcg) | 50 nm |
Underlap length (Lunderlap) | 10 nm |
Body thicknesses (Tbody) | 12 nm |
Gate dielectric (HfO2) thicknesses (Tox) | 3 nm |
Spacer (SiO2) thicknesses (Tspacer) | 30 nm |
Average grain size (Gsize) | 30 nm |
The SD of Gsize | 10 nm |
Source/Drain doping concentration | n-type, 1 × 1020 cm−3 |
Body doping concentration | p-type, 1 × 1018 cm−3 |
Main gate work-function (WFMG) | 4.85 eV |
Control gate work-function (W FCG) | 5.3 eV |
