Figure 6
We illustrate the area chart for our settling time experiments under different FWL formats (\(\langle 4, 4 \rangle\), \(\langle 8, 8 \rangle\), and \(\langle 16, 16 \rangle\)) and the number of attempts to synthesis the digital controllers from 1 to 15. As we can observe, the FWL format directly influences the number of attempts to synthesize these digital controllers considering the settling time specification.
