Figure 8
We illustrate the area chart for our experiments considering both settling time and overshoot under different FWL formats (\(\langle 4, 4 \rangle\), \(\langle 8, 8 \rangle\), and \(\langle 16, 16 \rangle\)) and the number of attempts to synthesis the digital controllers from 1 to 15. As we can observe, the FWL format directly influences the number of attempts to synthesize these digital controllers, considering settling time and overshoot as specification.
