Table 1 We show the experimental results considering settling time and overshoot specifications.

From: Formal synthesis of non-fragile state-feedback digital controllers considering performance requirements for step response

ID

Order

Settling time

Overshoot

Settling time and overshoot

<4,4>

<8,8>

<16,16>

<4,4>

<8,8>

<16,16>

<4,4>

<8,8>

<16,16>

R

T

R

T

R

T

R

T

R

T

R

T

R

T

R

T

R

T

1

2

S

1

S

1

S

3

S

5

S

1

S

1

S

1

S

1

S

3

2

3

S

1

S

1

S

4

F

TO

S

1

S

1

S

1

S

1

S

4

3

4

S

1

S

2

S

2

S

1

S

1

S

1

S

1

S

2

S

2

4

5

S

1

S

1

S

1

S

1

S

1

S

1

S

1

S

1

S

1

5

2

S

1

S

1

S

7

S

19

S

1

S

1

S

1

S

1

S

7

6

4

S

1

S

5

S

41

S

5

S

1

S

1

F

TO

F

TO

F

TO

7

4

S

1

S

1

S

1

F

TO

F

TO

F

TO

F

TO

F

TO

F

TO

8

2

S

1

S

1

S

3

S

3

S

3

S

1

S

1

S

1

S

1

9

3

S

1

S

1

S

3

S

1

S

1

S

1

S

22

S

1

S

3

10

4

S

3

S

2

S

6

S

1

S

1

S

1

S

3

S

2

S

2

11

5

S

1

S

1

S

1

S

1

S

1

S

1

S

12

S

1

S

1

12

2

F

MA

F

MA

F

MA

F

MA

F

MA

F

MA

F

MA

F

MA

F

MA

13

3

F

MA

F

MA

F

MA

F

MA

F

MA

F

MA

F

MA

F

MA

F

MA

14

4

S

1

S

1

S

1

F

TO

F

TO

F

TO

F

TO

F

TO

F

TO

15

2

S

1

S

1

S

1

S

1

S

1

S

1

S

1

S

1

S

1

  1. ID identifies each benchmark, Order indicates the number of continuous variables, R represents the result of the associated synthesis (successful or failed), T is the number of attempts to perform a synthesis procedure, MA means the maximum number of attempts has been reached, TO indicates that there was time-out during a specific execution, S means synthesis successful, F means synthesis failed.