Table 3 Experiments for settling time only.

From: Formal synthesis of non-fragile state-feedback digital controllers considering performance requirements for step response

Name

FWL

Result

Controller

Attempts

ET (dd:hh:mm:ss)

Buck converter

\(\langle 4,4 \rangle\)

SUCCESFUL

[0.312500, 0.062500]

6

7:00:48:00

Buck converter

\(\langle 8,8 \rangle\)

SUCCESFUL

[0.4687500000, 0.0078125000]

1

1:03:35:00

Buck converter

\(\langle 16,16 \rangle\)

SUCCESFUL

[0.437271118178390983, 0.011184692383179000]

1

1:04:53:00

Boost converter

\(\langle 4,4 \rangle\)

SUCCESFUL

[0.250000, 0.250000]

1

0:02:46:00

Boost converter

\(\langle 8,8 \rangle\)

SUCCESFUL

[0.3085937500, 0.2265625000]

1

0:02:01:00

Boost converter

\(\langle 16,16 \rangle\)

SUCCESFUL

[0.302810668955235007, 0.155609130864474005]

1

0:02:21:00

  1. It contains information about the converter name, FWL format, synthesis result, the synthesized controller, number of attempts to synthesize the controller, and total synthesis time.
Back to article page