Table 5 Experiments for both settling time and overshoot.

From: Formal synthesis of non-fragile state-feedback digital controllers considering performance requirements for step response

Name

FWL

Result

Controller

Attempts

ET (dd:hh:mm:ss)

Buck converter

\(\langle 4,4 \rangle\)

SUCCESFUL

[0.312500, 0.062500]

29

21:16:04:00

Buck converter

\(\langle 8,8 \rangle\)

SUCCESFUL

[0.4843750000, 0.0078125000]

1

1:01:05:00

Buck converter

\(\langle 16,16 \rangle\)

SUCCESFUL

[0.486404418961251028, 0.011489868164439001]

1

1:10:12:00

Boost converter

\(\langle 4,4 \rangle\)

SUCCESFUL

[0.250000, 0.187500]

1

0:02:04:00

Boost converter

\(\langle 8,8 \rangle\)

SUCCESFUL

[0.3125000000, 0.2812500000]

1

0:03:22:00

Boost converter

\(\langle 16,16 \rangle\)

SUCCESFUL

[0.304702758799047013, 0.188201904303042011]

1

0:02:47:00

  1. It contains information about the converter name, FWL format, synthesis result, the synthesized controller, number of attempts to synthesize the controller, and total synthesis time.
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