Figure 1
From: Scaling behavior of InAlN/GaN HEMTs on silicon for RF applications
(a) Schematic of fabricated InAlN/GaN HEMT; (b) Detailed device fabrication steps; (c) a plan-view scanning electron microscopy (SEM) image of the InAlN/GaN HEMT with a gate head length (Lhead) of 400 nm and a source-drain spacing (Lsd) of 600 nm; (d) A SEM image of T-shaped gate structure depicting a gate footprint of 50 nm.
