Figure 2

Coupling of two CMOS latch-based artificial Ising spins. Negative (Jij = − 1) and positive coupling (Jij = + 1) among the latches. The latch outputs (at the read terminal) always settle to the opposite (same) polarity when the negatively (positively) coupled, respectively, when the system is powered up. It is noted though that the exact output [i.e., whether Vout1 or Vout2 settle to 1 (= VDD) or 0 (= 0 V)] shows probabilistic behavior.