Figure 5 | Scientific Reports

Figure 5

From: CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays

Figure 5

CMOS Latch-based Ising Machine with FeFET-based Coupling. (a) Schematic of the FeFET array used to implement the coupling network and its interfacing with the CMOS-latches; negative coupling (Jij = − 1) is implemented here. (b) Half select VW/2 write scheme that is used to program the FeFET array. (c) A representative 4 node graph problem. (d) Time domain output of the write voltages and latch outputs for solving the representative problem in (c). (e) MaxCut solutions obtained for graphs of various size up to 50 nodes. The graphs were randomly generated; 30 graphs were tested in total (10 different graph configurations per node).

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