Figure 1
From: Stacked SiGe nanosheets p-FET for Sub-3 nm logic applications
Schematic representation of SiGe p-GAA FETs device fabrication.
Figure 1 | Scientific Reports
From: Stacked SiGe nanosheets p-FET for Sub-3 nm logic applications
Schematic representation of SiGe p-GAA FETs device fabrication.
