Figure 6
From: Extremely large area (88 mm × 88 mm) superconducting integrated circuit (ELASIC)
3D view of the ELASIC (active superconducting chip carrier) fabrication process starting from individual EX4 DUV reticle based circuits and their interconnection schemes to fabricate the ELASIC. Four EX4 DUV reticle based circuit layers (22 mm × 22 mm)are interconnected with an I-line reticle based circuit layer (44 mm × 44 mm) using sub-micron EX4 DUV vias (yellow). I line reticles (44 mm × 44 mm) are connected via stitching, ultimately allowing full connectivity of the 16 EX4 DUV reticles through the I-line circuit layer.
